The invention relates to a semiconductor chip that is flip-chip mounted in a substrate, and a semiconductor device on which the semiconductor chip is mounted, and more particularly, to a semiconductor chip and a semiconductor device that are suitably used for improvement of interconnection characteristics of mounting substrate.
With regard to the flip-chip mounting, in a substrate on which a semiconductor chip is mounted, a pad that is connected to a pad of the semiconductor chip is provided at a position facing the pad of the semiconductor chip. The pads are connected to each other through a bump and the like, thereby realizing electrical conduction. Hereinafter, the pad that is provided to the substrate to be connected to the semiconductor chip is referred to as “substrate pad”, and the pad on the semiconductor chip is simply referred to as “pad” or “chip pad”.
Along with improvement in a degree of integration, particularly, in a Large Scale Integrated circuit (LSI) such as a System on Chip (SoC), there is a tendency that a larger number of electrodes, that is, a larger number of pads is required in the semiconductor chip. With regard to an arrangement of the pad of the semiconductor chip, a so-called staggered arrangement, in which the pads are alternately arranged in two arrays at one side or both sides of input and output cells (IO cells) that are arranged in one array at each side of the semiconductor chip, is suggested. This is because the pads are significantly larger than the input and output cells, and thus the staggered arrangement has the best area efficiency.
JP-A-10-74790 discloses a technology of suppressing an area of a pad arrangement region in a case of arranging a plurality of pads on a surface of a semiconductor chip. At one side of an input and output buffer, the plurality of pads are arranged in a staggered shape in a plurality of arrays of two arrays or three or more arrays.
JP-A-2002-270779 discloses a technology of increasing an arrangement density of the TO pads without increasing a die size of the semiconductor chip. Input and output cells (IO cells) provided with an input and output circuit for electrical exchange with the outside are arranged in a ring shape at an outer peripheral portion of the semiconductor chip. The IO pads are arranged in a staggered shape with the IO cell arranged in a ring shape interposed therebetween.
In contrast, in the substrate on which the semiconductor chip is mounted, a substrate pad is arranged at a position facing the chip pad, and a through-hole via (hereinafter, simply referred to as “via”) that penetrates through the entirety of the substrate or an interconnection layer that constitutes the substrate toward an opposite surface is arranged, and is interconnected to the substrate pad using the same interconnection layer as the substrate pad. Along with reduction in size of the semiconductor chip and an increase in the number of pins, a pitch between the pads becomes narrow, and congestion of the via and the interconnection becomes apparent in the substrate. For example, the via cannot be arranged in the vicinity of the substrate pad to which the via is connected, and thus leading-out of the interconnection from the substrate pad to the via becomes longer. Therefore, there are problems in that an interconnection impedance increases, electrical characteristics deteriorate, and the like. In addition, interconnection characteristics on a layout surface deteriorate and an area of the substrate increases. Therefore, for example, in a case where the substrate is a mounting substrate of an LSI package, there are problems in that the size of the package that can be accommodated increases, and the like.
JP-A-2008-252126 discloses a technology of removing a cause of an increase in semiconductor chip size in a Chip Size Package (CSP) type semiconductor device that employs Pad on Element (POE) technique and a staggered electrode pad arrangement. More specifically, when referring to FIG. 2, abstract, and paragraphs [0011] to [0013] of JP-A-2008-252126, the following technology is disclosed. Adjacent to corner cells 11 on a surface of a semiconductor chip 10, input and output cells 12 are formed so as to line up along the peripheral portion and each electrode pad 13 is formed on each of the input and output cells 12. The electrode pads 13 constitute an inner pad array and an outer pad array to form the staggered pad arrangement. However, among the electrode pads 13 that constitute the inner pad array, an electrode pad arrangement in a predetermined range adjacent to both sides of the corner cells 11 are omitted to prevent complication of interconnection patterns 21 of a carrier 20 (corresponding to the substrate) which is bump-connected to the semiconductor chip 10, and vias 22.
JP-A-10-173087 discloses a layout of a plated interconnection in a package substrate of a Ball Grid Array (BGA). The plated interconnection in the package substrate represents an interconnection on a substrate which applies an electric potential necessary for an electrolytic treatment to all electrodes to send a current so as to electrolytically plate the electrodes on front and rear surfaces of the substrate. As shown in FIG. 2 of JP-A-10-173087, the plated interconnection 9 leads out to the outside from a bonding lead.